1. Field of the Invention
The present invention relates to digital signal latches, and in particular, to digital signal latches having some measure of self control based upon the incoming data and the previously latched data.
2. Description of the Related Art
As the needs for and uses of portable, battery-operated computers and other types of systems become more varied and widespread, techniques for reducing the power consumption, both static and dynamic, of the digital integrated circuits used in such systems becomes increasingly important. One area of technology currently receiving much attention is that of chips using complementary metal oxide semiconductor field effect transistors (CMOSFETs).
However, even as advances are made with respect to reducing the power consumption of such chips, a number of areas continue to pose significant problems. An example of one such area involves the dynamic power consumption of a typical CMOSFET chip due to the on-chip distribution and use of a clock signal. The on-chip capacitance due to the distribution of the clock signal is typically a significant portion of the total chip capacitance. Accordingly, the dynamic power consumed by such capacitance is a significant percentage of the total power dissipation for the chip.
Therefore, it would be desirable to have a technique by which the dynamic power consumption due to the on-chip distribution and use of a clock signal can be reduced without adversely affecting the operation of functionality of the chip.